Notes from the Wired
This is a website where I write articles on various topics that interest me, carving out a bit of cyberspace for myself.
You shouldn't believe anything I talk about — I use words entirely recreationally.
Most Recent
May. 11
Runtime Fault Localization in Deep Neural Network Accelerators
Paper Title: Runtime Fault Localization in Deep Neural Network Accelerators
Link to Paper: https://dl.acm.org/doi/10.1145/3770920
Date: 11. Nov 2025
Paper Type: Systolic arrays, deep neural network (DNN) accelerator, fault detection, fault localization, Checksums
Short Abstract: Systolic arrays are widely used for accelerating deep neural networks (DNNs) due to their high parallelism and data reuse efficiency. However, hardware faults in their numerous processing elements (PEs) can propagate errors and significantly degrade inference accuracy. The paper addresses the open challenge of fault localization in systolic arrays. It proposes a lightweight fault tolerance framework that performs both run-time fault detection and localization during normal operation. The approach uses functional data to generate checksums on-the-fly, eliminating the need for dedicated test patterns or system downtime. Reuslts: 100% fault detection and localization, 2% Area overhead.
May. 08
PRISONBREAK: Jailbreaking Large Language Models With at Most Twenty-Five Targeted Bit-flips
Paper Title: PRISONBREAK: Jailbreaking Large Language Models With at Most Twenty-Five Targeted Bit-flips
Link to Paper: https://arxiv.org/abs/2412.07192
Date: 10. Dec. 2024
Paper Type: LLM, Attack-Paper, Jailbreaking
Short Abstract: This paper is about jailbreaking LLMs, which means circumventing their protections against producing harmful content. To do this, their attack needs to flip at most 5–25 bits, which is 40× fewer bits than prior attacks and 20× faster than previous methods. They evaluate their method on 10 different open-source LLMs and achieve an attack success rate of 80–98%, with minimal utility and performance loss in the models.
May. 08
Resilience Assessment of Large Language Models under Transient Hardware Faults
Paper Title: Resilience Assessment of Large Language Models under Transient Hardware Faults
Link to Paper: https://ieeexplore.ieee.org/document/10301253
Date: 31. Jan 2023
Paper Type: LLM, Testing, Errors
Short Abstract: The paper investigates how resilient Large Language Models (LLMs) are to transient hardware faults (also called soft errors), such as random bit flips caused by cosmic rays, power fluctuations, or electromagnetic interference. This matters because LLMs are increasingly used in safety-critical systems. A transient fault may silently corrupt outputs without crashing the system, called a Silent Data Corruption (SDC).